Fast-in, slow-out (FISO) arrays are used in systems that acquire analog electrical signals at high sampling speeds. Such a system is disclosed in U.S. Pat. No. 5,144,525 to Saxe et al. for an "Analog Acquisition System Including a High Speed Timing Generator", hereby incorporated by reference. Another, similar, analog signal acquisition system, but one employing charge coupled devices (CCDs) instead of storage capacitors implemented using CMOS (Complementary Metal Oxide on Semiconductor) transistors, is disclosed in co-pending U.S. patent application Ser. No. 07/836,436 by the present inventor for a "FISO Analog Signal Acquisition System Employing CCD Array Storage", hereby incorporated by reference. Neither of these systems provide for FISO array redundancy.
Built-in redundancy is a technique for improving component yields by providing alternative circuitry that can be substituted for normal circuitry that does not operate properly. For example, in the manufacture of random access memories redundancy is typically used in both columns and rows to improve components yields.
FIG. 1 shows one approach that is used to provide row and column addressing redundancy in random access memories. In this very simplified example, two address lines a and b and their complements /a and /b are decoded by row decoders to provide row selection signals. The row decoder for regular rows can be as simple as the AND gate shown decoding the Row Enable #3 signal in this figure. The AND gate in the row decoder for Row Enable #3 is satisfied when a=1 and b=1 (a binary 3). To provide for the replacement of a defective row by a redundant row, the output of each regular row decoder is coupled to the row that it addresses by a laser burnable fuse link, such as the fuse link f5 shown for row 3.
In this approach, redundant rows are addressed by redundant row decoders that are more complex than the normal row decoders. The redundant row decoders receive as inputs all of the address lines and their complements. If all of the regular rows are operating properly and no redundant capabilities are needed, none of the fuse links shown in FIG. 1 need to be cut with a laser. Since both the address bits and their complements are connected to the gates of one of parallel transistors m1-m4, the presence of any address will turn on at least one of these transistors. When any of the transistors m1-m4 are on, they connect the redundant row address signal output to ground, keeping it inactive. Transistor m5 acts as a pull-up resistor, since its channel geometry is chosen to give it a relatively high resistance relative to the other transistors and it is always on because its gate is tied to ground and it is an PMOS transistor.
When there is a defect in one of the rows, that row is permanently disabled by the burning of fuse line f5. The redundant row decoder must then be programmed to respond to the address of the defective row or column. This is accomplished by burning the fuse links within the redundant row decoder that provide a ground path when the address is present that normally would activate the row that has been disabled. In the example here, where Row #3 is assumed to be defective and disabled, burning fuse links f2 and f4 dedicates the redundant row decoder to the task of being a Row #3 decoder substitute. With f2 and f4 gone, the presence of address "11" produces high signal levels on address lines a and b and low signal levels on the inverse address lines /a and/b. The lows on /a and /b keep transistors m1 and m3 turned off, while the absence of f2 and f4 keep m1 and m4 from conducting despite the high levels on their gates. The result is that during address "11" the redundant row output signal goes high.
FIG. 2A is a timing diagram that illustrates the case when all of the normal address rows are operational and no fuse links have been burned, while FIG. 2B is another timing diagram that illustrates the case when Row #3 is defective and fuse links f2, f4, and f5 have been cut to dedicate the redundant row to being a Row #3 substitute.
Obtaining redundancy in a FISO analog signal acquisition system must be approached differently, because the precise timing between successive sample and hold signals (also known as timing strobes) is extremely important. Since different columns in the array have to sample the input signal sequentially at times that are closely and evenly spaced apart, any practical method of providing redundancy must provide equivalent time pathways for each sample and hold signal and the acquired signal. Co-pending U.S. patent application Ser. No. 07/824,434 by the present inventor for a "High Speed Sample and Hold Signal Generator", hereby incorporated by reference, provides an example of how critical this timing requirement is and discloses circuitry for providing high speed sequential sample and hold signals whose temporal spacing is tightly controlled.
What is desired is an approach to providing sample and hold signal clocking to a redundant acquisition cell that maintains its timing relationship relative to the other samples in the acquisition. To maintain this timing relationship, the stray capacitance and other sources of delay in the redundant path must be exactly matched to those in the defective path.